Area-efficient FFT processor for MIMO-OFDM based SDR systems

IEICE Electronics Express

Gijung Yang²  Yunho Jung²  Seongjoo Lee¹  Soohyun Jang² 

[1] Department of Information and Communication Eng., Sejong University;School of Electronics, Telecommunication and Computer Eng., Korea Aerospace University

关键词: FFT;    MIMO-OFDM;    mixed-radix;    SDR;   

DOI  :  10.1587/elex.10.20130490

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(6)In this letter, an area-efficient FFT processor is proposed for MIMO-OFDM based SDR systems. The proposed FFT processor can support variable lengths of 64, 128, 256, 512, 1024, 1536 and 2048. By reducing the required number of non-trivial multipliers with a mixed-radix algorithm, the complexity of the proposed FFT processor is dramatically decreased. The proposed FFT processor was designed in a hardware description language (HDL) and synthesized to gate-level circuits using a 0.13µm CMOS standard cell library. With the proposed architecture, the gate count for the proposed FFT processor is 78.8K and the size of memory is 393.22Kbits, which are reduced by 40.9% and 19.7%, respectively, compared with the 4-channel radix-2 single-path delay feedback (R2SDF) with the 4-channel radix-3 SDF (R3SDF) FFT processor. Also, compared with the 4-channel radix-2 multi-path delay commutator (R2MDC) with the 4-channel R3SDF FFT processor, it is shown that the gate count and memory size are reduced by 33.8% and 18.5%, respectively.

【 授权许可】

Unknown