A 50-mA 1-nF Low-Voltage Low-Dropout VoltageRegulator for SoC Applications

ETRI Journal

关键词: frequency response;    system-on-chip;    low-voltage;    low-dropout;    voltage regulator;    CMOS integrated circuits;   

Others  :  1185912
DOI  :  10.4218/etrij.10.0109.0586

【 摘 要 】

In this paper, we present a low-voltage low-dropout voltage regulator (LDO) for a system-on-chip (SoC) application which, exploiting the multiplication of the Miller effect through the use of a current amplifier, is frequency compensated up to 1-nF capacitive load. The topology and the strategy adopted to design the LDO and the related compensation frequency network are described in detail. The LDO works with a supply voltage as low as 1.2 V and provides a maximum load current of 50 mA with a drop-out voltage of 200 mV: the total integrated compensation capacitance is about 40 pF. Measurement results as well as comparison with other SoC LDOs demonstrate the advantage of the proposed topology.

   

【 参考文献 】

• [1]G.A. Rincon-Mora and P.E. Allen, "A Low-Voltage, Low Quiescent Current, Low Drop Out Regulator," IEEE J. Solid-State Circuits, vol. 33, no. 1, Jan. 1998, pp. 36-44.
• [2]G.A. Rincon-Mora and P.E. Allen, "Optimized Frequency- Shaping Circuit Topologies for LDO’s," IEEE Trans. Circuits Syst. II, vol. 45, no. 6, Jun. 1998, pp. 703-708.
• [3]A. Low and P. Hasler, "Basics of Floating-Gate Low-Dropout Voltage Regulators," Proc. IEEE MWSCAS, Aug. 2000, pp. 1048-1051.
• [4]C.K. Chava and J. Silva-Martinez, "A Robust Frequency Compensation Scheme for LDO Regulators," Proc. IEEE ICECS, vol. 5, May 2002, pp. 825-828.
• [5]R. Tantawy and E.J. Brauer, "Performance Evaluation of CMOS Low Drop-out Voltage Regulators," Proc. IEEE MWSCAS, vol. 1, Jul. 2004, pp. 141-144.
• [6]P. Hazucha et al., "Area-Efficient Linear Regulator With Ultra-Fast Load Regulation," IEEE J. Solid-State Circuits, vol. 40, no. 4, Apr. 2005, pp. 933-940.
• [7]H.C. Lin, H.H. Wu, and T.Y. Chang, "An Active-Frequency Compensation Scheme for CMOS Low-Dropout Regulators With Transient-Response Improvement," IEEE Trans. Circuits Syst. II, vol. 55, no. 9, Sept. 2008, pp. 853-857.
• [8]H. Lee, P.K.T. Mok, and K.N. Leung, "Design of Low-Power Analog Drivers Based on Slew-Rate Enhancement Circuits for CMOS Low-Dropout Regulators," IEEE Trans. Circuits Syst. II, vol. 52, no. 9, Sept. 2005, pp. 563-567.
• [9]C.K. Chava and J. Silva-Martìnez, "A Frequency Compensation Scheme for LDO Voltage Regulators," IEEE Trans. Circuits Syst. I, vol. 51, no. 6, Jun. 2004, pp. 1041-1050.
• [10]X. Lai et al., "A 3-A CMOS Low-Dropout Regulator with Adaptive Miller Compensation," Analog Integr. Circuits Signal Process., vol. 49, no. 1, 2006, pp. 5-10.
• [11]G. Giustolisi, G. Palumbo, and E. Spitale, "Low-Voltage LDO Compensation Strategy based on Current Amplifiers," IEEE ISCAS, Seattle, USA, May 2008, pp. 2681-2684.
• [12]G. Giustolisi and G. Palumbo "Dynamic-Biased Capacitor-Free NMOS LDO," Electron. Letters, vol. 45, no. 22, Oct. 2009, pp. 1140-1141.
• [13]M. Loikkanen and J. Kostamovaara, "A Capacitor-Free CMOS Low-Dropout Regulator," Proc. IEEE ISCAS, May 2007, pp. 1915-1918.
• [14]T.Y. Man et al., "Development of Single-Transistor-Control LDO Based on Flipped Voltage Follower for SoC," IEEE Trans. Circuits Syst. I, vol. 55, no. 5, Jun. 2008, pp. 1392-1401.
• [15]T.Y. Man, P.K. T. Mok, and M. Chan, "A High Slew-Rate Push–Pull Output Amplifier for Low-Quiescent Current Low-Dropout Regulators With Transient-Response Improvement," IEEE Trans. Circuits Syst. II, vol. 54, no. 9, Sept. 2007, pp. 755-759.
• [16]K.N. Leung and P.K.T. Mok, "A Capacitor-Free CMOS Low-Dropout Regulator with Damping-Factor-Control Frequency Compensation," IEEE J. Solid-State Circuits, vol. 38, no. 10, Oct. 2003, pp. 1691-1702.
• [17]R.J. Milliken, J. Silva-Martìnez, and E. Sànchez-Sinencio, "Full On-Chip CMOS Low-Dropout Voltage Regulator," IEEE Trans. Circuits Syst. I, vol. 54, no. 9, Sept. 2007, pp. 1879-1890.
• [18]S.K. Lau et al., "A Low-Dropout Regulator for SoC With Q-Reduction," IEEE J. Solid-State Circuits, vol. 42, no. 3, Mar. 2007, pp. 658-664.
• [19]G. Giustolisi, G. Palumbo, and E. Spitale, "LDO Compensation Strategy Based on Current Buffer/Amplifiers," Proc. IEEE ECCTD, Seville (Spain), Aug. 2007, pp. 116-119.
• [20]G. Palmisano and G. Palumbo, "A Compensation Strategy for Two-Stage CMOS Opamps Based on Current Buffer," IEEE Trans. Circuits Syst. I, vol. 44, no. 3, Mar. 1997, pp. 257-262.
• [21]G. Palumbo and S. Pennisi, Feedback Amplifiers (Theory and Design), Kluwer Academic Publishers, 2002.
• [22]W. Aloisi, G. Palumbo, and S. Pennisi, "Design Methodology of Miller Frequency Compensation with Current Buffer/Amplifier," IET Circuits Devices Syst., vol. 2, no. 2, Apr. 2008, pp. 227-233.
• [23]G.A. Rincon-Mora, "Active Capacitor Multiplier in Miller-Compensated Circuits," IEEE J. Solid-State Circuits, vol. 35, no. 1, Jan. 2000, pp. 26-32.
• [24]M. Al-Shyoukh, H. Lee, and R. Perez, "A Transient-Enhanced Low-Quiescent Current Low-Dropout Regulator With Buffer Impedance Attenuation," IEEE J. Solid-State Circuits, vol. 42, no. 8, Aug. 2007, pp. 1732-1742.
• [25]W. Oh and B. Bakkaloglu, "A CMOS Low-Dropout Regulator With Current-Mode Feedback Buffer Amplifier," IEEE Trans. Circuits Syst. II, vol. 54, no. 10, Oct. 2007, pp. 922-926.
• [26]W. Oh et al., "A CMOS Low Noise, Chopper Stabilized Low-Dropout Regulator With Current-Mode Feedback Error Amplifier," IEEE Trans. Circuits Syst. I, vol. 55, no. 10, Nov. 2008, pp. 3006-3015.
• [27]W. Chen, W.H. Ki, and P.K.T. Mok, "Dual-Loop Feedback for Fast Low Dropout Regulators," Proc. IEEE PESC, vol. 3, Jun. 2001, pp. 1265-1269.
• [28]G. Giustolisi and G. Palumbo, "An Approach to Test the Open-Loop Parameters of Feedback Amplifiers," IEEE Trans. Circuits Syst. I, vol. 49, no. 1, Jan. 2002, pp. 70-75.
• [29]A. J. Lòpez-Martìn et al., "Low-Voltage Super Class AB CMOS OTA Cells with Very High Slew Rate and Power Efficiency," IEEE J. Solid-State Circuits, vol. 40, no. 5, May 2005, pp. 1068-1077.
• [30]10.1109/JSSC.2005.845977