Low-Power 512-Bit EEPROM Designed for UHF RFID Tag Chip

ETRI Journal

关键词: charge pump;    dual power;    sensing scheme;    tag chip;    UHF RFID;    EEPROM;    Low-power;   

Others  :  1185672
DOI  :  10.4218/etrij.08.0107.0154

【 摘 要 】

In this paper, the design of a low-power 512-bit synchronous EEPROM for a passive UHF RFID tag chip is presented. We apply low-power schemes, such as dual power supply voltage (VDD=1.5 V and VDDP=2.5 V), clocked inverter sensing, voltage-up converter, I/O interface, and Dickson charge pump using Schottky diode. An EEPROM is fabricated with the 0.25 µm EEPROM process. Power dissipation is 32.78 µW in the read cycle and 78.05 µW in the write cycle. The layout size is 449.3 µm × 480.67 µm.

   

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