Low Complexity Hardware Architectures for Wavelet Transforms: A Survey

International Conference on Materials Engineering and Science

Hasan, Khamees Khalaf^1,2 ; Dham, Mahmood Ali A.^1,2 ; Nawaf, Shahir Fleyeh^1,2

Salahaddin Province, P.O. Box (45), Tikrit, Iraq^1

Department of Electrical Engineering, Tikrit University, Salahaddin, Iraq^2

关键词: Algorithm implementation;    Communication energy;    Computation intensives;    Hardware acceleration;    Hardware architecture;    JPEG 2000 standard;    Low computational loads;    Wavelet based image compression;   

Others  :  https://iopscience.iop.org/article/10.1088/1757-899X/454/1/012051/pdf
DOI  :  10.1088/1757-899X/454/1/012051

来源: IOP

【 摘 要 】

Presently, the major focus is on developing techniques to efficiently decrease hardware expenditure as well as hardware complications while realizing the requirements for a real-time system. The enhancement of Discrete Wavelet Transforms DWT's hardware modelling is still a relatively novel subject of research. Such areas comprise developing an effective hardware acceleration of the implementation of the DWT of the JPEG2000 standard, to construct a practical model and to deal with the computational and communication energy limitations of the image compression system. This paper emphasizes a comprehensive survey to develop necessary solutions to enhance the potential and capacity of DWT's computation-intensive nature algorithm implementation, particularly for low power image compression applications. The paper focuses on the major factors in order to lower the DWT principal energy consuming phase, given the energy consumption of the whole wavelet based image compression. These factors may possibly encompass some hardware-based features, such as basic coding features, low memory requirement, and low computational load. In combination with this research, other paper areas are also being investigated.