Aging analysis of high performance FinFET flip-flop under Dynamic NBTI simulation configuration

International Conference on Applied Electronic and Engineering 2017

无线电电子学;工业技术

Zainudin, M.F.^1,2 ; Hussin, H.^1,2 ; Halim, A.K.^1 ; Karim, J.^1

Faculty of Electrical Engineering, Universiti Teknologi Mara (UiTM), Selangor Shah Alam

40450, Malaysia^1

Integrated Microelectronics Systems and Applications Research Group, Universiti Teknologi Mara (UiTM), Selangor Shah Alam

40450, Malaysia^2

关键词: Circuit performance;    Circuit reliability;    Electrical parameter;    High-performance circuits;    Negative bias temperature instability (NBTI);    Negative stress;    Simulation configuration;    Stress condition;   

Others  :  https://iopscience.iop.org/article/10.1088/1757-899X/341/1/012012/pdf
DOI  :  10.1088/1757-899X/341/1/012012

学科分类：工业工程学

来源: IOP

【 摘 要 】

A mechanism known as Negative-bias Temperature Instability (NBTI) degrades a main electrical parameters of a circuit especially in terms of performance. So far, the circuit design available at present are only focussed on high performance circuit without considering the circuit reliability and robustness. In this paper, the main circuit performances of high performance FinFET flip-flop such as delay time, and power were studied with the presence of the NBTI degradation. The aging analysis was verified using a 16nm High Performance Predictive Technology Model (PTM) based on different commands available at Synopsys HSPICE. The results shown that the circuit under the longer dynamic NBTI simulation produces the highest impact in the increasing of gate delay and decrease in the average power reduction from a fresh simulation until the aged stress time under a nominal condition. In addition, the circuit performance under a varied stress condition such as temperature and negative stress gate bias were also studied.