Implementation of digital equality comparator circuit on memristive memory crossbar array using material implication logic

International Conference on Applied Electronic and Engineering 2017

无线电电子学;工业技术

Haron, Adib^1 ; Mahdzair, Fazren^1 ; Luqman, Anas^1 ; Osman, Nazmie^1 ; Mutalib Al Junid, Syed Abdul^1

Electronic Architecture and Application Research Group (EArA), Faculty of Electrical Engineering, Universiti Teknologi, MARA, Shah Alam Selangor

40450, Malaysia^1

关键词: Area utilization;    Data-intensive application;    Limited bandwidth;    Logic operations;    Neumann architecture;    Parallel mapping;    Processing time;    Resistive switching;   

Others  :  https://iopscience.iop.org/article/10.1088/1757-899X/341/1/012025/pdf
DOI  :  10.1088/1757-899X/341/1/012025

学科分类：工业工程学

来源: IOP

【 摘 要 】

One of the most significant constraints of Von Neumann architecture is the limited bandwidth between memory and processor. The cost to move data back and forth between memory and processor is considerably higher than the computation in the processor itself. This architecture significantly impacts the Big Data and data-intensive application such as DNA analysis comparison which spend most of the processing time to move data. Recently, the in-memory processing concept was proposed, which is based on the capability to perform the logic operation on the physical memory structure using a crossbar topology and non-volatile resistive-switching memristor technology. This paper proposes a scheme to map digital equality comparator circuit on memristive memory crossbar array. The 2-bit, 4-bit, 8-bit, 16-bit, 32-bit, and 64-bit of equality comparator circuit are mapped on memristive memory crossbar array by using material implication logic in a sequential and parallel method. The simulation results show that, for the 64-bit word size, the parallel mapping exhibits 2.8× better performance in total execution time than sequential mapping but has a trade-off in terms of energy consumption and area utilization. Meanwhile, the total crossbar area can be reduced by 1.2× for sequential mapping and 1.5× for parallel mapping both by using the overlapping technique.