The Research on Key Blocks of Multi-phase Clock Circuit

2017 2nd Asia Conference on Power and Electrical Engineering

能源学;电工学

Liu, Y.C.^1 ; Wang, J.Y.^1 ; Wang, H.L.^1 ; Lv, F.X.^1,2

Air and Missile Defense Academy of Air Force Engineering University, Xi'an

710051, China^1

Institute of Microelectronic, Tsinghua University, Bei'jing

100084, China^2

关键词: Clock generation circuits;    Differential structure;    Dynamic performance;    Polyphase structures;    Sinusoidal input signals;    Sinusoidal signals;    Square wave signals;    Track-and-hold amplifiers;   

Others  :  https://iopscience.iop.org/article/10.1088/1757-899X/199/1/012106/pdf
DOI  :  10.1088/1757-899X/199/1/012106

来源: IOP

【 摘 要 】

Based on the process of IHP 130nm SiGe BiCMOS, a four-phase 2GHz clock generation circuit was proposed. Proposed clock generation circuit consisted of a polyphase phase shifter which applied characteristic of RC network and a differential clock buffer. Considering the bandwidth shortage of single stage polyphase structure, a three stages cascade polyphase structure was proposed to broaden circuit bandwidth. HBT based differential clock buffer replaced single-ended MOSFET based clock buffer to achieve higher clock frequency. At the same time, differential structure could also effectively reduce clock signal feedthrough which would flow into sampling capacitance and deteriorate dynamic performance of the circuit. The layouts of every block were designed highly symmetric to eliminate phase errors. Simulation results showed that four channels clock square-wave signal, whose difference of phase was 90°, could be generated when differentially inputting 2GHz sinusoidal signal. The rising time of proposed clock was 9.7ps, and the phase error between different clocks was 2.2°. 8GHz sinusoidal input signal could be successfully tracked and held when applying the proposed clock into four channels Track and Hold Amplifiers.