Linearity analysis of single-ended SAR ADC with split capacitive DAC

1st International Telecommunication Conference "Advanced Micro- and Nanoelectronic Systems and Technologies"

无线电电子学

Osipov, Dmitry^1 ; Malankin, Evgeny^2 ; Shumikhin, Vitaly^2

Institute of Electrodynamics and Microelectronics (ITEM), University of Bremen, Otto-Hahn-Allee NW 1, Bremen

28359, Germany^1

ASIC Lab, National Research Nuclear University, MEPhI, Kashirskoe highway 31, Moscow

115409, Russia^2

关键词: Capacitive dac;    Capacitor arrays;    CMOS processs;    Differential nonlinearity;    Sampling rates;    Signal frequencies;    Split-capacitor arrays;    Variable sampling rates;   

Others  :  https://iopscience.iop.org/article/10.1088/1757-899X/151/1/012014/pdf
DOI  :  10.1088/1757-899X/151/1/012014

来源: IOP

【 摘 要 】

This paper proposes the design of a 6-bit single-ended SAR ADC with a variable sampling rate at a maximum achievable speed of 50 MS/s. The SAR ADC utilizes the split capacitor array DAC with a non-conventional split-capacitor value. The influence of switches in the capacitive DAC on the ADC's non-linearity is analysed. According to the fulfilled analysis the recommendations for switches and capacitor array dimensioning are given to provide a minimum differential non-linearity (DNL). At a sampling rate of 50 MS/s, the SAR ADC achieves an ENOB of 5.4 bit at an input signal frequency of 1 MHz and consumes 1.2 mW at a 1.8 V power supply, resulting in an energy efficiency of 568 fJ/conv.-step. The SAR ADC was simulated with parasitics in a standard 180nm CMOS process.