High-Speed Superconductive Decimation Filter for Sigma-Delta Analog to Digital Converter

29th International Symposium on Superconductivity

Wakamatsu, Tomu^1 ; Yamanashi, Yuki^1 ; Yoshikawa, Nobuyuki^1

Department of Electrical and Computer Engineering, Yokohama National University, 79-5 Tokiwadai, Hodogaya, Yokohama, Japan^1

关键词: Analog-to-digital;    Decimation filter;    Low speed operation;    Nb fabrication process;    Operating frequency;    Operation frequency;    Sampling frequencies;    Sigma-delta analog-to-digital converters;   

Others  :  https://iopscience.iop.org/article/10.1088/1742-6596/871/1/012068/pdf
DOI  :  10.1088/1742-6596/871/1/012068

来源: IOP

【 摘 要 】

A superconducting decimation filter is required to convert high-speed output data from a superconducting sigma-delta analog to digital (A/D) modulator to low-speed data for data acquisition by room-temperature electronics. Because the operating frequency of the conventional superconducting decimation filter is lower than that of the maximum operation frequency of A/D modulator, the system performance of the superconducting A/D converter is limited by the decimation filter. We propose a decimation filter that can operate at the sampling frequency of the A/D modulator by hybridizing a shift-register-based and a counter-based decimation filters. The investigated decimation filter can be implemented with a practical circuit area. We designed and tested the investigated decimation filter. The simulation result indicates that the maximum operation frequency of the designed decimation filter is 39.8 GHz assuming the 2.5 kA/cm2Nb fabrication process. We experimentally confirmed the low-speed operation of the designed decimation filter with the bias margin of 93.8%-110.8%.