Development of the read-out ASIC for muon chambers

International Conference on Particle Physics and Astrophysics

Atkin, E.^1 ; Bulbakov, I.^1 ; Gusev, A.^1 ; Malankin, E.^1 ; Normanov, D.^1 ; Sagdiev, I.^1 ; Shumikhin, V.^1 ; Shumkin, O.^1 ; Ivanov, P.^1 ; Vinogradov, S.^1 ; Voronin, A.^2 ; Samsonov, V.^1 ; Ivanov, V.^1

National Research Nuclear University MEPhI (Moscow Engineering Physics Institute), Kashirskoe highway 31, Moscow

115409, Russia^1

Skobeltsyn Institute of Nuclear Physics Lomonosov, Moscow State University, Leninskie gory 1/2, Moscow

119991, Russia^2

关键词: Analog processing;    Area-Efficient;    Differential comparators;    Dynamic range;    Front end;    Hit rate;    Muon chamber;    Serializers;   

Others  :  https://iopscience.iop.org/article/10.1088/1742-6596/675/4/042030/pdf
DOI  :  10.1088/1742-6596/675/4/042030

来源: IOP

【 摘 要 】

A front-end prototype ASIC for muon chambers is presented. ASIC was designed and prototyped in the CMOS UMC MMRF 180 nm process via Europractice. The chip includes 8 analog processing channels, each consisting of a preamplifier, two shapers (fast and slow), differential comparator and an area efficient 6 bit SAR ADC with 1.2 mW power consumption at 50 Msps. The chip also includes the threshold DAC and digital serializer. The design has the following features: dynamic range of 100 fC, channel hit rate of 2 MHz, ENC of 1000 e- at 50 pF, power consumption of 10 mW per channel, 6 bit SAR ADC.