The new CMS DAQ system for LHC operation after 2014 (DAQ2)

20th International Conference on Computing in High Energy and Nuclear Physics

物理学;计算机科学

Bauer, Gerry^6 ; Bawej, Tomasz^2 ; Behrens, Ulf^1 ; Branson, James^4 ; Chaze, Olivier^2 ; Cittolin, Sergio^4 ; Coarasa, Jose Antonio^2 ; Darlea, Georgiana-Lavinia^6 ; Deldicque, Christian^2 ; Dobson, Marc^2 ; Dupont, Aymeric^2 ; Erhan, Samim^3 ; Gigi, Dominique^2 ; Glege, Frank^2 ; Gomez-Ceballos, Guillelmo^6 ; Gomez-Reino, Robert^2 ; Hartl, Christian^2 ; Hegeman, Jeroen^2 ; Holzner, Andre^4 ; Masetti, Lorenzo^2 ; Meijers, Frans^2 ; Meschi, Emilio^2 ; Mommsen, Remigius K.^5 ; Morovic, Srecko^2,7 ; Nunez-Barranco-Fernandez, Carlos^2 ; O'Dell, Vivian^5 ; Orsini, Luciano^2 ; Ozga, Wojciech^2 ; Paus, Christoph^6 ; Petrucci, Andrea^2 ; Pieri, Marco^4 ; Racz, Attila^2 ; Raginel, Olivier^6 ; Sakulin, Hannes^2 ; Sani, Matteo^4 ; Schwick, Christoph^2 ; Spataru, Andrei Cristian^2 ; Stieger, Benjamin^2 ; Sumorok, Konstanty^6 ; Veverka, Jan^6 ; Wakefield, Christopher Colin^2 ; Zejdl, Petr^2

DESY, Hamburg, Germany^1

CERN, Geneva, Switzerland^2

University of California, Los Angeles, Los Angeles

CA, United States^3

University of California, San Diego, San Diego

CA, United States^4

FNAL, Chicago

IL, United States^5

Massachusetts Institute of Technology, Cambridge

MA, United States^6

Institute Rudjer Boskovic, Zagreb, Croatia^7

关键词: Aggregate throughput;    Compact Muon solenoids;    Data acquisition system;    Multi-core cpu architectures;    Networking technology;    Off-detector electronics;    Storage infrastructure;    Throughput capacities;   

Others  :  https://iopscience.iop.org/article/10.1088/1742-6596/513/1/012014/pdf
DOI  :  10.1088/1742-6596/513/1/012014

学科分类：计算机科学（综合）

来源: IOP

【 摘 要 】

The Data Acquisition system of the Compact Muon Solenoid experiment at CERN assembles events at a rate of 100 kHz, transporting event data at an aggregate throughput of 100 GByte/s. We are presenting the design of the 2nd generation DAQ system, including studies of the event builder based on advanced networking technologies such as 10 and 40 Gbit/s Ethernet and 56 Gbit/s FDR Infiniband and exploitation of multicore CPU architectures. By the time the LHC restarts after the 2013/14 shutdown, the current compute nodes, networking, and storage infrastructure will have reached the end of their lifetime. In order to handle higher LHC luminosities and event pileup, a number of sub-detectors will be upgraded, increase the number of readout channels and replace the off-detector readout electronics with a μTCA implementation. The second generation DAQ system, foreseen for 2014, will need to accommodate the readout of both existing and new off-detector electronics and provide an increased throughput capacity. Advances in storage technology could make it feasible to write the output of the event builder to (RAM or SSD) disks and implement the HLT processing entirely file based.