Implementation of a PC-based Level 0 Trigger Processor for the NA62 Experiment

20th International Conference on Computing in High Energy and Nuclear Physics

物理学;计算机科学

Pivanti, M.^1 ; Schifano, S.F.^2 ; Dalpiaz, P.^1 ; Gamberini, E.^1 ; Gianoli, A.^1 ; Sozzi, M.^3

Physics Department, INFN, Ferrara University, V. Saragat 1, Ferrara

44122, Italy^1

Mathematics and Informatics Department, INFN, Ferrara University, V. Saragat 1, Ferrara

44122, Italy^2

Physics Department, INFN, Pisa University, Largo Pontecorvo 3, Pisa

56127, Italy^3

关键词: Fundamental component;    High energy physics experiments;    PC-based;   

Others  :  https://iopscience.iop.org/article/10.1088/1742-6596/513/1/012008/pdf
DOI  :  10.1088/1742-6596/513/1/012008

学科分类：计算机科学（综合）

来源: IOP

【 摘 要 】

Lowest level (sometimes called Level 0, L0) triggers are fundamental components in high energy physics experiments, and yet they are quite often custom-made. Even when using FPGAs to achieve better flexibility in modifying and maintaining, small changes require hardware reconfiguration and changes to the algorithm logic could be constrained by the hardware. For these reasons we are developing for the NA62 experiment at CERN a L0-trigger based on the use of a PC and commodity FPGA development board.