ESD protection circuit for V-band RF applications in a 65nm CMOS technology

2019 2nd International Conference on Composite Materials Science and Technology

Lowaton, Allenn C.^1 ; Bañez, Lemuel Fil L.^1

Microelectronics Laboratory, Electrical Engineering and Technology Department, Mindanao State University, Iligan Institute of Technology, Iligan City, Philippines^1

关键词: 65nm CMOS technology;    ESD protection circuit;    Human body modeling;    Nano-scale CMOS;    Parasitic capacitance;    pMOS transistors;    Radio frequency circuit;    RF applications;   

Others  :  https://iopscience.iop.org/article/10.1088/1757-899X/600/1/012025/pdf
DOI  :  10.1088/1757-899X/600/1/012025

来源: IOP

【 摘 要 】

To apply radio frequency circuits, nanoscale CMOS technologies are greatly used but this consequence to a thinner gate oxide and silicided drain/source. With this, the electrostatic discharge (ESD) robustness of RF circuits will be much more degraded. Therefore, there is a need for an ESD protection circuit design in RF circuits against ESD damages. In this paper, the proposed ESD protection circuit is presented with concept based silicon-controlled rectifier (SCR) device, two diodes, PMOS transistor and an inductor to efficiently provide protection for radio-frequency (RF) circuits from ESD damages in nanoscale CMOS process. The concept based SCR device is aided with an inductor to provide efficient ESD path discharge to the SCR device. Moreover, the inductor is used to resonate out the parasitic capacitance generated by the ESD protection circuit at the preferred frequency. In addition, the proposed ESD protection circuit is implemented to a low noise amplifier (LNA) at 60-GHz frequency within an efficient area. Furthermore, the ESD protection circuit is simulated to achieve over 2-kV human body model ESD robustness with good RF performances on LNA in 65-nm CMOS technology.