1 Logic area reduction using the deep trench isolation technique based on 40 nm embedded PCM process [期刊论文]
来源:IEICE Electronics Express , 2017
作者:Zhitang Song;Yuan Du;Weiliang Jing;等
关键词:logic area reduction;NSL;...
使用许可:CC BY
1 Logic area reduction using the deep trench isolation technique based on 40 nm embedded PCM process [期刊论文]
来源:IEICE Electronics Express , 2017
作者:Zhitang Song;Yuan Du;Weiliang Jing;等
关键词:logic area reduction;NSL;...
使用许可:CC BY