Next generation TV have been developed according to the advances of display technology. It is expected to have high resolution above 4K and to support additional functions such as 3D display and multi-view for enriching user experience. Efficient codec have been also developed in order to process high resolution videos faster than existing codecs, and High Efficiency Video Coding (HEVC) is the most representative one. HEVC is considered as the most appropriate video codec for next generation TV since HEVC provides more efficient video compression and higher video quality compared to existing codecs. However, HEVC reference software cannot fully utilize multi-core system resources, which is the trend of recent SoC design, because it is implemented to be executed sequentially on single-core. In this paper, we propose parallelization technique of HEVC decoder based on task graph model. Our technique aims for providing flexible software model to support design space exploration for the design of next generation TV SoC, and to increase throughput performance by parallel processing on multi-core SoC platform. In addition to task graph based technique, we propose Single Instruction Multi Data (SIMD) based optimization. Performance increase by our technique is verified with experimental results. We achieves speed-up of 15.59 for 2560x1600 sequences and 15.85 for 3840x2160 sequences, compared to base reference software.
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