캐시 및 ECC 내장을 통한 DDR4 생산성 향상에 관한 연구

디램;신뢰성;오버헤드 특성;디램 내장 오류 정정 부호;디디알4;620

융합과학기술대학원 융합과학부 ;

University:서울대학교 대학원

关键词: 디램;    신뢰성;    오버헤드 특성;    디램 내장 오류 정정 부호;    디디알4;    620;   

Others  :  http://s-space.snu.ac.kr/bitstream/10371/133172/1/000000024942.pdf

美国|英语

来源: Seoul National University Open Repository

【 摘 要 】

During the past few decades, steady DRAM scaling has enabledhigher capacity and faster speed of DRAM. However, faulty DRAMcells have been more frequent through the scaling, becoming a majorproblem for maintaining DRAM productivity. Faulty cells inducefluctuation in DRAM retention time and lead to DRAM devicefailures. Conventional solutions to repair faulty cells includepopulating redundant cells and adopting ECC (Error-Correcting Code).However, these become a burden of DRAM productivity due to higharea overheads. Uniform-randomly distributed single bit errors are themajority of the faulty cells. Therefore, the conventional solutions areinefficient because they require too many normal cells per faulty cells and induce degradation in DRAM performance as the needed logicgates lie in critical paths.This thesis proposes a novel architecture for DRAM faulty cells toimprove DRAM productivity over conventional solutions and identifiesthe possibilities of implementing ECC in DDR4. We add a smallSRAM cache in DRAM device to repair faulty cells instead of normalDRAM cells. The area of an SRAM cell is higher than that of aDRAM cell, but implementing a cache in DRAM is area efficientcompared to sacrificing rows of normal DRAM cells peruniform-randomly distributed single bit error. Also, using a bloomfilter reduces the energy overhead by filtering most accesses to theSRAM cache that would miss anyway. Especially, this SRAM cacheand Bloom filter operate in parallel with normal DRAM accesses,which does not degrade DRAM performance. In implementing ECC inDDR4, the increasing codeword sizes reduce the area overhead, butread-modify-write operation induces the degradation of DRAMperformance. And it requires a feature to report the result of ECCback to a memory controller. DRAM scaling makes manufacturershave serious concerns due to faulty cells. Therefore, this thesis alsostudies the effect of our solutions in accordance with the proportionof faulty cells in DRAM and the possibilities of implementing ECC inDDR4 devices.