Spacer Optimization from Gate-Induced Drain Leakage Perspective in 3-nm Node Device

Gate-Induced Drain Leakage;Spacer;Ultra-scaled device;Nano-plate FET;Spacer material;structure Optimization;621.3

University:서울대학교 대학원

关键词: Gate-Induced Drain Leakage;    Spacer;    Ultra-scaled device;    Nano-plate FET;    Spacer material;    structure Optimization;    621.3;   

Others  :  http://s-space.snu.ac.kr/bitstream/10371/161055/1/000000156159.pdf

美国|英语

来源: Seoul National University Open Repository

【 摘 要 】

In this paper, structural and material optimization of gate sidewall spacer in the perspective of off-state leakage current was performed in a 3-nm node Nanoplate FET (NPFET). First, gate induced drain leakage (GIDL) current, a dominant factor of off-state leakage current, and active performance (on-current, on/off current ratio) were co-optimized according to structural correlation of gate sidewall spacer with other structural components such as gate, source, and drain length. Furthermore, by comparing structural relations between gate-spacer and S/D-spacer, a better structural optimization method was proposed. Second, structural and material optimization of asymmetric spacer structure was performed. If the spacer is designed asymmetrically, GIDL current was reduced by 72% through the optimization of the asymmetric spacer, resulting in a 67% reduction in the overall off-sate leakage current. Then, the on/off current ratio got enhanced by 4.7 times. Finally, dual-k spacer structure was investigated using the variety of materials along the high-k spacer length. To verifying the effect of the dual-k spacer on GIDL current, the GIDL characteristic according to the inner spacer material, which mainly affect the GIDL characteristic in dual-k spacer structure, were compared. Optimization of the gate sidewall spacer, proposed in this paper, showed effectively reduced GIDL current and enhanced active performance.