Programmable Analog Techniques For Precision Analog Circuits, Low-Power Signal Processing and On-Chip Learning

Programmable multipliers;Adaptive filters;Voltage references;Offset cancellation;Floating-gate transistors;Synapse

Srinivasan, Venkatesh ; Electrical and Computer Engineering

University:Georgia Institute of Technology

Department:Electrical and Computer Engineering

关键词: Programmable multipliers;    Adaptive filters;    Voltage references;    Offset cancellation;    Floating-gate transistors;    Synapse;   

Others  :  https://smartech.gatech.edu/bitstream/1853/11588/1/srinivasan_venkatesh_200608_phd.pdf

美国|英语

来源: SMARTech Repository

【 摘 要 】

In this work, programmable analog techniques using floating-gate transistors have been developed to design precision analog circuits, low-power signal processing primitives and adaptive systems that learn on-chip. Traditional analog implementations lack programmability with the result that issues such as mismatch are corrected at the expense of area. Techniques have been proposed that use floating-gate transistors as an integral part of the circuit of interest to provide both programmability and the ability to correct for mismatch. Traditionally, signal processing has been performed in the digital domain with analog circuits handling the interface with the outside world. Such a partitioning of responsibilities is inefficient as signal processing involves repeated multiplication and addition operations that are both very power efficient in the analog domain. Using programmable analog techniques, fundamental signal processing primitives such as multipliers have been developed in a low-power fashion while preserving accuracy. This results in a paradigm shift in signal processing. A co-operative analog/digital signal processing framework is now possible such that the partitioning of tasks between the analog and digital domains is performed in a power efficient manner. Complex signal processing tasks such as adaptive filtering that learn the weight coefficients are implemented by exploiting the non-linearities inherent with floating-gate programming. The resulting floating-gate synapses are compact, low-power and offer the benefits of non-volatile weight storage. In summary, this research involves developing techniques for improving analog circuit performance and in developing power-efficient techniques for signal processing and on-chip learning.