Low-cost and efficient architectural support for correctness and performance debugging

Scalability in multi-cores;Debugging;Computer architecture

Venkataramani, Guru Prasadh V. ; Computing

University:Georgia Institute of Technology

Department:Computing

关键词: Scalability in multi-cores;    Debugging;    Computer architecture;   

Others  :  https://smartech.gatech.edu/bitstream/1853/31747/1/venkataramani_guruprasadh_v_200912.pdf

美国|英语

来源: SMARTech Repository

【 摘 要 】

With rapid growth in computer hardware technologies and architectures, software programs have become increasingly complex and error-prone. This software complexity has resulted in program crashes and even security threats. Correctness Debugging is making sure that the program does not exhibit any unintended behavior at runtime. A fully correct program without good performance does not lend any commercial success to the software product. Performance Debugging ensures good performance on hardware platforms. A number of prior debugging solutions either suffer from huge performance overheads or incur high implementation costs. We propose low-cost and efficient hardware solutions that target three specific correctness and performance problems, namely, memory debugging, taint propagation and comprehensive cache miss classification. Experiments show that our mechanisms incur low performance overheads and can be designed with minimal changes to existing processor hardware. While architects invest time and resources into designing high-end architectures, we show that it is equally important to incorporate useful debugging features into these processors in order to enhance the ease of use for programmers.