Improving processor efficiency by exploiting common-case behaviors of memory instructions

Power;Performance;Computer architecture;Processor

Subramaniam, Samantika ; Computing

University:Georgia Institute of Technology

Department:Computing

关键词: Power;    Performance;    Computer architecture;    Processor;   

Others  :  https://smartech.gatech.edu/bitstream/1853/28165/1/subramaniam_samantika_200905_phd.pdf

美国|英语

来源: SMARTech Repository

【 摘 要 】

Processor efficiency can be described with the help of a number of  desirableeffects or metrics, for example, performance, power, area, designcomplexity and access latency.These metrics serve as valuable tools used in designing new processorsand they also act as  effective standards for comparing current processors.Various factors impact the efficiency of modern out-of-order processorsand one important factor is the manner in which instructions are processedthrough the processor pipeline.In this dissertation research, we study the impact of load and storeinstructions(collectively known as memory instructions) on processor efficiency, and show how to improve efficiency by exploiting common-case or predictable patterns in the behavior of memory instructions.The memory behavior patterns that we focus on in our research arethe predictability of memory dependences, the predictability indata forwarding patterns,  predictability in instruction criticality andconservativenessin resource allocation anddeallocation policies.We first design a scalable  and high-performance memory dependencepredictor and then applyaccurate memory dependence prediction to improve the efficiency ofthe fetch engine of a simultaneous multi-threaded processor.We then use predictable data forwarding patterns to eliminate power-hungry hardware in the processor with no loss in performance.  We then move to studying instruction criticality to improve processor efficiency. We study the behavior of critical load instructions and propose applications that can be optimized using  predictable,load-criticality information. Finally, we explore conventional techniques forallocation and deallocation of critical structures that process memory instructions and propose newtechniques to optimize the same.  Our new designs have the potential to reduce the power and the area required by processors significantly without losing performance, which lead to efficient designs of processors.