Impact of size effects and anomalous skin effect on metallic wires as GSI interconnects

Bit-rate limit;Surface scattering;Gain boundary scattering;Copper;GSI;VLSI interconnect;Anomalous skin effect;Size effects

Sarvari, Reza ; Electrical and Computer Engineering

University:Georgia Institute of Technology

Department:Electrical and Computer Engineering

关键词: Bit-rate limit;    Surface scattering;    Gain boundary scattering;    Copper;    GSI;    VLSI interconnect;    Anomalous skin effect;    Size effects;   

Others  :  https://smartech.gatech.edu/bitstream/1853/31636/1/sarvari_reza_200812_phd.pdf

美国|英语

来源: SMARTech Repository

【 摘 要 】

The 2006 International Technology Roadmap for Semiconductors projects that for 2020, interconnects will be as narrow as 14 nm and will operate at frequencies as high as 50GHz. For a wire that operates at ultra-high frequencies, such that skin depth and the mean free path of the electrons are in the same order, skin effect and surface scattering should be considered simultaneously. This is known as the anomalous skin effect (ASE).The objective of this work is to identify the challenges and opportunities for using GSI interconnects in the nanometer and GHz regime. The increase in the resistivity of a thin wire caused by the ASE is studied. The delay of a digital transmission line resulting from this effect is modeled. Compact models are presented for the bit-rate limit of transmission lines using a general form of resistance that for the first time simultaneously considers dc resistance, skin effect, and surface scattering. A conventional low-loss approximation that is only valid for fast rising signals is also relaxed.The impact of size effects on the design of multi-level interconnect networks is studied. For high-performance chips at the 18 nm technology node, it is shown that despite a more than four times increase in the resistivity of copper for minimum-size interconnects, the increase in the number of metal levels is negligible (less than 7%), and interconnects that will be affected most are so short that their impact on chip performance is inconsequential. It is shown that for low-cost applications where very few wiring pitches are normally used, the number of metal levels needed to compensate for the impact of size effects on the average rc delay of a copper interconnect is drastically high. An optimization methodology has been presented for power distribution interconnects at the local level. For a given IR drop budget, compact models are presented for the optimal widths of power and ground lines in the first two metal levels for which the total metal area used for power distribution is minimized.