Electroplated multi-path compliant copper interconnects for flip-chip packages

Compliant interconnects;Flip-chip technology;Delta interconnects;Copper/Low-k compatible technology;Low die stress;White bump solution;MEMS;CMOS compatible

Okereke, Raphael Ifeanyi ; Sitaraman, Suresh K. Mechanical Engineering Ume, Ifeanyi C. Sulchek, Todd Swaminathan, Madhavan Bakir, Muhannad S. ; Sitaraman, Suresh K.

University:Georgia Institute of Technology

Department:Mechanical Engineering

关键词: Compliant interconnects;    Flip-chip technology;    Delta interconnects;    Copper/Low-k compatible technology;    Low die stress;    White bump solution;    MEMS;    CMOS compatible;   

Others  :  https://smartech.gatech.edu/bitstream/1853/51800/1/OKEREKE-DISSERTATION-2014.pdf

美国|英语

来源: SMARTech Repository

【 摘 要 】

The international technology roadmap for semiconductors (ITRS) 2012 report foresees the use of porous dielectric materials with a low dielectric constant in conjunction with copper interconnects as a way to reduce the resistive-capacitive (RC) delay in microelectronic applications. However, the introduction of pores in the dielectric not only serves as stress raisers but also diminishes the structural strength of the material. The challenge therefore with the implementation of low-k dielectrics for high-performance flip-chip packages is to create a reliable die to organic substrate interconnect solution which induces low stresses on the die to prevent the cohesive cracking and the interfacial delamination of the dielectric material.Potential interconnect solutions that meet this challenge are MEMS-like compliant freestanding micro-structures. These structures are designed to work as spring-like elements which allow the free lateral and out-of-plane motion between the silicon die and the organic substrate under assembly conditions as well as under thermal or power cycling. Thus, the focus of this research is to design, fabricate, and characterize electrically and mechanically an innovative compliant interconnect approach that addresses these challenges.The proposed interconnect is scalable in dimensions and pitch, and consists multiple electrical paths which will provide redundancy against interconnect failure. The multi-path design employs parallel electrical paths which effectively split a larger cross-sectional area into several smaller areas making the overall design more compliant than otherwise. This research proposes wafer-level, high-yield, CMOS-compatible fabrication procedure using sequential photolithography and copper electroplating. The proposed interconnects are symmetric and are amenable to easy reflow assembly to substrates. The mechanical compliance of the fabricated structures is studied through nano-indentation, while the electrical characteristics are assessed through fabricated prototypes. Thexvithermo-mechanical reliability of compliant interconnects is also demonstrated. Lastly, the dimensional scalability of the interconnects is also demonstrated.