Design for pre-bond testability in 3D integrated circuits

Shorting probes;Test wrapper design;3D-MAPS;DFT;Design for test;3D integration;Pre-bond test;Test architecture

Lewis, Dean Leon ; Electrical and Computer Engineering

University:Georgia Institute of Technology

Department:Electrical and Computer Engineering

关键词: Shorting probes;    Test wrapper design;    3D-MAPS;    DFT;    Design for test;    3D integration;    Pre-bond test;    Test architecture;   

Others  :  https://smartech.gatech.edu/bitstream/1853/45756/1/lewis_dean_l_201212_phd.pdf

美国|英语

来源: SMARTech Repository

【 摘 要 】

In this dissertation we propose several DFT techniques specific to 3Dstacked IC systems. The goal has explicitly been to create techniques thatintegrate easily with existing IC test systems. Specifically, this meansutilizing scan- and wrapper-based techniques, two foundationsof the digital IC test industry.First, we describe a general test architecture for 3D ICs. In thisarchitecture, each tier of a 3D design is wrapped in test control logic that both manages tier testpre-bond and integrates the tier into the large test architecture post-bond.We describe a new kind of boundary scan to provide the necessary test control and observation of the partial circuits, and we proposea new design methodology for test hardcore that ensures both pre-bond functionalityand post-bond optimality. We present the application of these techniquestothe 3D-MAPS test vehicle, which has proven their effectiveness.Second, we extend these DFT techniques to circuit-partitioned designs. We findthat boundary scan design is generally sufficient, but that some 3D designs requirespecial DFT treatment. Most importantly, we demonstrate that the functionalpartitioning inherent in 3D design can potentially decrease the total test costof verifying a circuit.Third, we present a new CAD algorithm for designing 3D test wrappers. This algorithmco-designs the pre-bond and post-bond wrappers to simultaneously minimize testtime and routing cost. On average, our algorithm utilizes over 90% of the wiresin both the pre-bond and post-bond wrappers.Finally, we look at the 3D vias themselves to develop a low-cost, high-volumepre-bond test methodology appropriate for production-level test. We describethe shorting probes methodology, wherein large test probes are used to contactmultiple small 3D vias. This technique is an all-digital test method thatintegrates seamlessly into existing test flows. Ourexperimental results demonstrate two key facts: neither the large capacitanceof the probe tips nor the process variation in the 3D vias and the probe tipssignificantly hinders the testability of the circuits.Taken together, this body of work defines a complete test methodology fortesting 3D ICs pre-bond, eliminating one of the key hurdles to thecommercialization of 3D technology.