Configurable analog hardware for neuromorphic Bayesian inference and least-squares solutions

Regularized least-squares;Sparse approximation;Analog circuits;FPAA;Neural network;Hopfield network;Locally competitive algorithm (LCA)

Shapero, Samuel Andre ; Hasler, Jennifer Electrical and Computer Engineering Anderson, David Eliasmith, Christopher Rozell, Christopher Stanley, Garrett ; Hasler, Jennifer

University:Georgia Institute of Technology

Department:Electrical and Computer Engineering

关键词: Regularized least-squares;    Sparse approximation;    Analog circuits;    FPAA;    Neural network;    Hopfield network;    Locally competitive algorithm (LCA);   

Others  :  https://smartech.gatech.edu/bitstream/1853/51719/1/shapero_samuel_a_201305_phd.pdf

美国|英语

来源: SMARTech Repository

【 摘 要 】

Sparse approximation is a Bayesian inference program with a wide number of signal processing applications, such as Compressed Sensing recovery used in medical imaging. Previous sparse coding implementations relied on digital algorithms whose power consumption and performance scale poorly with problem size, rendering them unsuitable for portable applications, and a bottleneck in high speed applications. A novel analog architecture, implementing the Locally Competitive Algorithm (LCA), was designed and programmed onto a Field Programmable Analog Arrays (FPAAs), using floating gate transistors to set the analog parameters. A network of 6 coefficients was demonstrated to converge to similar values as a digital sparse approximation algorithm, but with better power and performance scaling. A rate encoded spiking algorithm was then developed, which was shown to converge to similar values as the LCA. A second novel architecture was designed and programmed on an FPAA implementing the spiking version of the LCA with integrate and fire neurons. A network of 18 neurons converged on similar values as a digital sparse approximation algorithm, with even better performance and power efficiency than the non-spiking network. Novel algorithms were created to increase floating gate programming speed by more than two orders of magnitude, and reduce programming error from device mismatch. A new FPAA chip was designed and tested which allowed for rapid interfacing and additional improvements in accuracy. Finally, a neuromorphic chip was designed, containing 400 integrate and fire neurons, and capable of converging on a sparse approximation solution in 10 microseconds, over 1000 times faster than the best digital solution.