Design of an Array Based Row Decoder and Self-referencing Sense Amplifier for Large Scale Resistance Change Style Molecular Memories.

dummy bitline;dummy;level shifter

Tyagi, Itisha ; Paul D Franzon, Committee Chair,Wm. Rhett Davis, Committee Member,Douglas Reeves, Committee Member,Tyagi, Itisha ; Paul D Franzon ; Committee Chair ; Wm. Rhett Davis ; Committee Member ; Douglas Reeves ; Committee Member

University:North Carolina State University

关键词: dummy bitline;    dummy;    level shifter;   

Others  :  https://repository.lib.ncsu.edu/bitstream/handle/1840.16/806/etd.pdf?sequence=1&isAllowed=y

美国|英语

来源: null

【 摘 要 】

Molecular memory refers to a data storage device in which a bit can be stored on a single molecule or atom. This technology holds the potential to provide significant area and density advantages compared to CMOS technology. The molecules, held between two lithographically defined electrodes, exhibit two conductivity states as appropriate voltage levels are applied across the electrodes.However, it is difficult to fabricate or synthesize a regular, precise and repeatable molecular memory array. The peripheral circuit around these arrays needs to take into account the variability in the devices, lack of isolation between them, and the interconnect resistances. This work presents a circuit configuration of row decoders and sense amplifier used to address and access data from such a molecular memory. A Row decoder is implemented as a NAND array. The Sense Amplifier uses a self-referencing technique to detect varying "0" and "1" voltage levels occurring due to device variation. The selfreferencing technique needs the "Read" operation to consist of 2 "Reads", a "Reset" and a "Write", and this mechanism has been automated. The concept of dummy bit-line is implemented to improve the Signal to Noise ratio during read operation. The circuit is implemented around memory arrays up to 1kbit in size, which run at clock frequency of 250 kHz. The peripheral circuit design is done using the TSMC 0.18μm technology. Some of the techniques of CMOS⁄Nano co-design are also explored to seek a possible nanoscale layout solution for the circuit.