Optimum gate arrangements for MOS standardized layouts

Field Effect Transistor (FET)

Robbins, David H. ; Mayeda ; Watura

关键词: Field Effect Transistor (FET);   

Others  :  https://www.ideals.illinois.edu/bitstream/handle/2142/45707/Robbins_David.pdf?sequence=2&isAllowed=y

美国|英语

来源: The Illinois Digital Environment for Access to Learning and Scholarship

【 摘 要 】

Optimization of size is an important topic of research in the engineering of digital circuits. The field effect transistor (FET) is making an important contribution in thisarea. In this paper, the basic properties of the FET which pertain to digital circuits will be examined. The problems associated with the physical layout of large integrated circuits using FETs will also be discussed and a standardized method of layout will be reviewed. A simple procedure for optimizing chip area when using this standardized layoutmethod will be developed and illustrated.