An evaluation framework for massively parallel accelerator processors

Accelerator;Chip Mulitprocessor;Parallel Processing

Johnson, Daniel R. ; Patel ; Sanjay J.

关键词: Accelerator;    Chip Mulitprocessor;    Parallel Processing;   

Others  :  https://www.ideals.illinois.edu/bitstream/handle/2142/24396/johnson_daniel.pdf?sequence=1&isAllowed=y

美国|英语

来源: The Illinois Digital Environment for Access to Learning and Scholarship

【 摘 要 】

In this thesis, I describe the evaluation framework for Rigel,a 1024-core single-chip accelerator architecture designed forhigh throughput on visual computing and scientific workloads.I present an integrated evaluation framework for investigating co-designedarchitecture, compilers, programming models, and RTL implementationfor massively parallel chip multiprocessors (CMPs).The research objective of the Rigel project,designing a prototype thousand-core chip,led to the development of the framework presented in this thesis.I describe the tools and techniques which enabled this work.The goal of this thesis is not to evaluate specific design tradeoffs, but todescribe the tools we have developed for making these decisions.I motivate and describe our integrated performance simulator, code generator,and RTL implementation for evaluation of a novel 1024-core accelerator architecture.I demonstrate the utility of a flexible hardware-software interfacesupporting an evolving ISA for architectural design space exploration.Although I present experiences related to a particular design,the methods applied and lessons learned are more broadly applicable.I summarize some of the published work which this framework has enabled.