Novel many-core architectures for energy-efficiency

Power constraints;Dark silicon;Near-threshold voltage;Many-core architectures;Process variations;Static random-access memory (SRAM) fault models;Wear-Out

Karpuzcu, Rahmet

关键词: Power constraints;    Dark silicon;    Near-threshold voltage;    Many-core architectures;    Process variations;    Static random-access memory (SRAM) fault models;    Wear-Out;   

Others  :  https://www.ideals.illinois.edu/bitstream/handle/2142/34560/Karpuzcu_Rahmet.pdf?sequence=1&isAllowed=y

美国|英语

来源: The Illinois Digital Environment for Access to Learning and Scholarship

【 摘 要 】

Ideal CMOS device scaling relies on scaling voltages down with lithographicdimensions at every technology generation. This gives rise to faster circuitsdue to higher frequency and smaller silicon area for the same functionality.The dynamic power density - equivalently, dynamic power, if the chip area isfixed - stays constant. Static power density, on the other hand, increases.Inearly generations, however, since the share of static power was practicallynegligible, dynamic power density staying constant translated to total powerdensity staying constant.This picture has changed recently. To keep the growth of the static power undercontrol, the decrease in the threshold voltage has practically stopped.This,in turn, has prevented the supply voltage from scaling.The end effect is anincreasing power density over generations, giving rise to the power wall:Processor chips can include more cores and accelerators than can be active atany given time - and the situation is getting worse.This effect, utilizationwall or dark silicon, as induced by the power wall, presents a fundamentalchallenge that is transforming the many-core architecture landscape.This dissertation attempts to address the key implication of the power wallproblem, dark silicon, in two novel and promising ways: By (1) trading off theprocessor service life for power and performance - the BubbleWrap many-core, and(2) exploring near-threshold voltage operation from an architectural perspective- the Polyomino many-core. The BubbleWrap many-core assumes as many cores on chip as CMOS transistordensity scaling trends suggest, and exploits the resulting implicit redundancy- as not all of the cores can be powered on simultaneously - to extractmaximum performance by trading off power and service life on a per-core basis.To achieve this, BubbleWrap continuously tunes the supply voltage within thecourse of each core's service life, leveraging any aging-induced guard-bandinstantaneously left, rendering one of the following regimes of operation:Minimize power at the same performance level and processor service life; attainthe highest performance for the same service life while respecting the givenpower budget; or attain even higher performance for a shorter service life whilerespecting the given power budget. Effectively, BubbleWrap runs each core at acloser-to-optimal operating point by always aggressively using up all theaging-induced guard-band that the designers have included - preventing any wasteof it.Another way to dim dark silicon is reducing the supply voltage to a value onlyslightly higher than the threshold voltage. This regime is called near-thresholdvoltage (NTV) computing (NTC), as opposed to conventional super-thresholdvoltage (STV) computing (STC).A major drawback of NTC is the highersusceptibility to parametric variations, namely the deviation of deviceparameters from their nominal values.To address parametric variations inpresent and future NTV designs, this dissertation builds on an existing model ofvariations at STV and develops the first architectural model of processvariations at NTV. Further, using the model, this dissertation demonstrates thatfacilitating multiple on-chip voltage domains to handle parametric variationswill not be cost effective in near-future NTV designs. With this insight, thisdissertation introduces Polyomino, a simple many-core architecture which caneffectively cope with variations at NTV.Polyomino eschews multiple voltagedomains and relies on fine-grain frequency domains to optimize execution undervariations.Thanks to Polyomino's simplicity, a variation-aware scheduler caneffectively assign clusters of cores to jobs.