Toward realizing power scalable and energy proportional high-speed wireline links

energy proportional;rapid-on/off;Phase locked loops (PLLs);multiplying delay locked loop (MDLL);delay locked loop;transceiver;Input/Output (I/O);serial link;temperature sensor;LC oscillator;LC oscillator

Anand, Tejasvi

关键词: energy proportional;    rapid-on/off;    Phase locked loops (PLLs);    multiplying delay locked loop (MDLL);    delay locked loop;    transceiver;    Input/Output (I/O);    serial link;    temperature sensor;    LC oscillator;    LC oscillator;   

Others  :  https://www.ideals.illinois.edu/bitstream/handle/2142/89205/ANAND-DISSERTATION-2015.pdf?sequence=1&isAllowed=y

美国|英语

来源: The Illinois Digital Environment for Access to Learning and Scholarship

【 摘 要 】

Growing computational demand and proliferation of cloud computing has placed high-speedserial links at the center stage. Due to saturating energy efficiency improvements over thelast five years, increasing the data throughput comes at the cost of power consumption. Conventionally, serial link power can be reduced by optimizing individual building blocks such asoutput drivers, receiver, or clock generation and distribution. However, this approach yieldsvery limited efficiency improvement. This dissertation takes an alternative approach towardreducing the serial link power. Instead of optimizing the power of individual building blocks,power of the entire serial link is reduced by exploiting serial link usage by the applications.It has been demonstrated that serial links in servers are underutilized. On average, theyare used only 15% of the time, i.e. these links are idle for approximately 85% of the time.Conventional links consume power during idle periods to maintain synchronization betweenthe transmitter and the receiver. However, by powering-off the link when idle and poweringit back when needed, power consumption of the serial link can be scaled proportionally toits utilization. This approach of rapid power state transitioning is known as the rapid-on/offapproach. For the rapid-on/off to be effective, ideally the power-on time, off-state power,and power state transition energy must all be close to zero. However, in practice, it is verydifficult to achieve these ideal conditions. Work presented in this dissertation addresses thesechallenges.When this research work was started (2011-12), there were only a couple of research papersavailable in the area of rapid-on/off links. Systematic study or design of a rapid power statetransitioning in serial links was not available in the literature. Since rapid-on/off withnanoseconds granularity is not a standard in any wireline communication, even the populartest equipment does not support testing any such feature, neither any formal measurement methodology was available. All these circumstances made the beginning difficult. However,these challenges provided a unique opportunity to explore new architectural techniques andidentify trade-offs. The key contributions of this dissertation are as follows.The first and foremost contribution is understanding the underlying limitations of saturating energy efficiency improvements in serial links and why there is a compelling need tofind alternative ways to reduce the serial link power.The second contribution is to identify potential power saving techniques and evaluate thechallenges they pose and the opportunities they present.The third contribution is the design of a 5Gb/s transmitter with a rapid-on/off feature.The transmitter achieves rapid-on/off capability in voltage mode output driver by usinga fast-digital regulator, and in the clock multiplier by accurate frequency pre-setting andperiodic reference insertion. To ease timing requirements, an improved edge replacementlogic circuit for the clock multiplier is proposed. Mathematical modeling of power-on timeas a function of various circuit parameters is also discussed. The proposed transmitterdemonstrates energy proportional operation over wide variations of link utilization, and is,therefore, suitable for energy efficient links. Fabricated in 90nm CMOS technology, thevoltage mode driver, and the clock multiplier achieve power-on-time of only 2ns and 10ns,respectively. This dissertation highlights key trade-off in the clock multiplier architecture,to achieve fast power-on-lock capability at the cost of jitter performance.The fourth contribution is the design of a 7GHz rapid-on/off LC-PLL based clock multi-plier. The phase locked loop (PLL) based multiplier was developed to overcome the limita-tions of the MDLL based approach. Proposed temperature compensated LC-PLL achievespower-on-lock in 1ns.The fifth and biggest contribution of this dissertation is the design of a 7Gb/s embeddedclock transceiver, which achieves rapid-on/off capability in LC-PLL, current-mode transmit-ter and receiver. It was the first reported design of a complete transceiver, with an embeddedclock architecture, having rapid-on/off capability. Background phase calibration technique inPLL and CDR phase calibration logic in the receiver enable instantaneous lock on power-on.The proposed transceiver demonstrates power scalability with a wide range of link utiliza-tion and, therefore, helps in improving overall system efficiency. Fabricated in 65nm CMOS technology, the 7Gb/s transceiver achieves power-on-lock in less than 20ns. The transceiverachieves power scaling by 44x (63.7mW-to-1.43mW) and energy efficiency degradation byonly 2.2x (9.1pJ/bit-to-20.5pJ/bit), when the effective data rate (link utilization) changesby 100x (7Gb/s-to-70Mb/s).The sixth and final contribution is the design of a temperature sensor to compensatethe frequency drifts due to temperature variations, during long power-off periods, in thefast power-on-lock LC-PLL. The proposed self-referenced VCO-based temperature sensoris designed with all digital logic gates and achieves low supply sensitivity. This sensor issuitable for integration in processor and DRAM environments. The proposed sensor workson the principle of directly converting temperature information to frequency and finallyto digital bits. A novel sensing technique is proposed in which temperature informationis acquired by creating a threshold voltage difference between the transistors used in theoscillators. Reduced supply sensitivity is achieved by employing junction capacitance, andthe overhead of voltage regulators and an external ideal reference frequency is avoided. Theeffect of VCO phase noise on the sensor resolution is mathematically evaluated. Fabricatedin the 65nm CMOS process, the prototype can operate with a supply ranging from 0.85Vto 1.1V, and it achieves a supply sensitivity of 0.034oC/mV and an inaccuracy of ±0.9oCand ±2.3oC from 0-100oC after 2-point calibration, with and without static nonlinearitycorrection, respectively. It achieves a resolution of 0.3oC, resolution FoM of 0.3(nJ/conv)res2 ,and measurement (conversion) time of 6.5μs.