Energy-efficient wireline transceivers

Data communication;High speed serial link;Wireline transceiver;Continuous-ratereceiver;Clock and data recovery;Reference-less CDR;Digital CDR;Jitter peaking;Decouple JTRAN/JTOL;Phase-rotating PLL;Phase interpolator;Digitally controlled oscillator (DCO);Supply regulator;Active repeater;Optical links;Energy proportional links;Matched source synchronous clocking;Rapid on/off clock generator;Multiplaying delay-locked loop (MDLL);Dynamic voltage and frequency scaling (DVFS);Rapid on/off (ROO);Alpha-power law model;Leakage power;Exit latency

Shu, Guanghua

关键词: Data communication;    High speed serial link;    Wireline transceiver;    Continuous-ratereceiver;    Clock and data recovery;    Reference-less CDR;    Digital CDR;    Jitter peaking;    Decouple JTRAN/JTOL;    Phase-rotating PLL;    Phase interpolator;    Digitally controlled oscillator (DCO);    Supply regulator;    Active repeater;    Optical links;    Energy proportional links;    Matched source synchronous clocking;    Rapid on/off clock generator;    Multiplaying delay-locked loop (MDLL);    Dynamic voltage and frequency scaling (DVFS);    Rapid on/off (ROO);    Alpha-power law model;    Leakage power;    Exit latency;   

Others  :  https://www.ideals.illinois.edu/bitstream/handle/2142/95549/SHU-DISSERTATION-2016.pdf?sequence=1&isAllowed=y

美国|英语

来源: The Illinois Digital Environment for Access to Learning and Scholarship

【 摘 要 】

Power-efficient wireline transceivers are highly demanded by many applications in high performance computation and communication systems. Apart from transferring a wide range of data rates to satisfy the interconnect bandwidth requirement, the transceivers have very tight power budget and are expected to be fully integrated. This thesis explores enabling techniques to implement such transceivers in both circuit and system levels. Specifically, three prototypes will be presented: (1) a 5Gb/s reference-less clock and data recovery circuit (CDR) using phase-rotating phase-locked loop (PRPLL) to conduct phase control so as to break several fundamental trade-offs in conventional receivers; (2) a 4-10.5Gb/s continuous-rate CDR with novel frequency acquisition scheme based on bang-bang phase detector (BBPD) and a ring oscillator-based fractional-N PLL as the low noise wide range DCO in the CDR loop; (3) a source-synchronous energy-proportional link with dynamic voltage and frequency scaling (DVFS) and rapid on/off (ROO) techniques to cut the link power wastage at system level. The receiver/transceiver architectures are highly digital and address the requirements of new receiver architecture development, wide operating range, and low power/area consumption while being fully integrated. Experimental results obtained from the prototypes attest the effectiveness of the proposed techniques.