Successive-approximation-register based quantizer design for high-speed delta-sigma modulators

Analog-to-digital converters;High speed successive approximation register (SAR);Delta-sigma modulators;Quantizer;Medium resolution successive approximation register (SAR);Time-interleaved successive approximation register (TI SAR);Time-interleaved analog-to-digital converter (ADC);Higher order delta-sigma modulator design;Delta-sigma simulink models;Successive approximation register analog-to-digital converter (SAR ADC) design

Shah, Aarti Mahesh Kumar ; Radhakrishnan ; Chandrasekhar

关键词: Analog-to-digital converters;    High speed successive approximation register (SAR);    Delta-sigma modulators;    Quantizer;    Medium resolution successive approximation register (SAR);    Time-interleaved successive approximation register (TI SAR);    Time-interleaved analog-to-digital converter (ADC);    Higher order delta-sigma modulator design;    Delta-sigma simulink models;    Successive approximation register analog-to-digital converter (SAR ADC) design;   

Others  :  https://www.ideals.illinois.edu/bitstream/handle/2142/97465/SHAH-THESIS-2017.pdf?sequence=1&isAllowed=y

美国|英语

来源: The Illinois Digital Environment for Access to Learning and Scholarship

【 摘 要 】

High-speed delta-sigma modulators are in high demand for applications such as wire-line and wireless communications, medical imaging, RF receivers and high-definition video processing. A high-speed delta-sigma modulator requires that all components of the delta-sigma loop operate at the desired high frequency. For this reason, it is essential that the quantizer used in the delta-sigma loop operate at a high sampling frequency. This thesis focuses on the design of high-speed time-interleaved multi-bit successive-approximation-register (SAR) quantizers. Design techniques for high-speed medium-resolution SAR analog-to-digital converters (ADCs) using synchronous SAR logic are proposed.Four-bit and 8-bit 5 GS/s SAR ADCs have been implemented in 65 nm CMOS using 8-channel and 16-channel time-interleaving respectively. The 4-bit SAR ADC achieves SNR of 24.3 dB, figure-of-merit (FoM) of 638 fJ/conversion-step and 42.6 mW power consumption, while the 8-bit SAR ADC achieves SNR of 41.5 dB, FoM of 191 fJ/conversion-step and 92.8 mW power consumption. High-speed operation is achieved by optimizing the critical path in the SAR ADC loop. A sampling network with a split-array with unit bridge capacitor topology is used to reduce the area of the sampling network and switch drivers.