Receiver equalization for a 10 gigabit per second high-speed serial link in 65 nm CMOS technology

DFE, CTLE, Equalizer, Signal Integrity, High-speed serial link

Rajwardan, Ashwarya ; Schutt-Ainé ; José E.

关键词: DFE, CTLE, Equalizer, Signal Integrity, High-speed serial link;   

Others  :  https://www.ideals.illinois.edu/bitstream/handle/2142/104803/RAJWARDAN-THESIS-2019.pdf?sequence=1&isAllowed=y

美国|英语

来源: The Illinois Digital Environment for Access to Learning and Scholarship

【 摘 要 】

This thesis addresses the receiver equalization techniques for a 10 Gbps USB 3.1 link in 65 nm CMOS technology. Two types of equalizers are implemented: a continuous time linear equalizer (CTLE) and a 1-tap full-rate decision feedback equalizer (DFE). The combined CTLE and DFE architecture is simulated with an rms receiver clock jitter of 5.3 ps and achieves a BER < 10E−12 while consuming 3.3 mW at the Nyquist frequency of 5 GHz.