The impact of soft errors in logic and its commercialisation in ARM IP

T Technology (General);TK Electrical engineering. Electronics Nuclear engineering;Q Science (General)

Graham, Derek ; Roy, Scott A.

University:University of Glasgow

Department:School of Engineering

关键词: dependability, reliability, soft errors, neutrons, alpha particles, soft error rate, SER, single event upset, SEU, bus interconnect, AMBA, SoC, logical masking, fault injection;   

Others  :  http://theses.gla.ac.uk/2663/1/2011grahamengd.pdf

来源: University of Glasgow

【 摘 要 】

The significance of soft errors in logic has grown because of reduced memoryvulnerability and the shrinking dimensions of semiconductor technology coupledwith the increasing amount of logic integrated into a chip. Consequently, someof ARM’s customers are concerned about how soft errors on the bus interconnectwill affect the dependability of their systems, since the interconnect is a criticalhub of communication in a SoC and represents a substantial and growing amountof logic. With the rising complexity of their systems, the interconnect willbecome larger and more complex in the future, adding to their concern. In thiswork the impact of soft errors on the bus interconnect logic was investigatedand a product was developed to ameliorate the effects of such errors on ARM’scustomers’ products.Methods to measure the SER of ARM IP were investigated by focusing onlogical masking, which is a component in the calculation of the SER. The effectthat the topology of a combinatorial logic circuit has on its logical masking ratewas considered by performing gate-level statistical fault injection on differentimplementations of adder circuits. Significant variation in logical masking wasfound ranging from a factor of 3.1 at a synthesis frequency of 100 MHz to a factorof 2.1 at 900 MHz. This difference is explained in an original way by correlatinglogical masking with the circuit’s path length and fan-out. These propertiescould be used to create a static method of measuring the logical masking ratherthan the current time-consuming method of dynamic simulation. Additionally,nearly 30% of faults injected cause more than one error, which means that thecombinational SER will be underestimated if research does not take gate fan-outinto consideration. Using this methodology a circuit designer can now base hischoice or development of a circuit on its reliability as well as its performance,power, and area. Studying the variation in the factors that affect the SER isimportant to ensure accuracy in addressing customer requirements.Although it is important to consider the rate of soft error occurrence, in thiswork the impact of errors is demonstrated to be critical. Using protocol-levelfault injection it is shown that faults on the ARM AXI bus interconnect can havea serious effect on the reliability of the entire SoC such as deadlock, memorycorruption, or undefined behaviour. Using a fault-path traversal algorithm,it is demonstrated that traditional error detection codes are not sufficient atpreventing these failures when faults occur on certain AXI bus signals. This ledto the development of novel fault tolerant methods that provide protection forthese identified signals. Based on these developments, a product was proposed foran add-on to the AXI bus interconnect that can detect, correct, and report logicsoft errors without changing the AMBA standard or the customer’s connectingIP.