Quarc: an architecture for efficient on-chip communication

QA75 Electronic computers. Computer science

Moadeli, Mahmoud ; Vanderbauwhede, Wim

University:University of Glasgow

Department:School of Computing Science

关键词: Network-on-chip, Quarc, multicast, performance modelling, quality of service;   

Others  :  http://theses.gla.ac.uk/1991/1/2010moadeliackpdh.pdf

来源: University of Glasgow

【 摘 要 】

The exponential downscaling of the feature size has enforced a paradigm shift from computation-based design to communication-based design in system on chip development. Buses, the traditional communication architecture in systems on chip, are incapable of addressing the increasing bandwidth requirements of future large systems.Networks on chip have emerged as an interconnection architecture offering unique solutions to the technological and design issues related to communication in future systems on chip. The transition from buses as a shared medium to networks on chip as a segmented medium has given rise to new challenges in system on chip realm.By leveraging the shared nature of the communication medium, buses have been highly efficient in delivering multicast communication. The segmented nature of networks, however, inhibits the multicast messages to be delivered as efficiently by networks on chip. Relying on extensive research on multicast communication in parallel computers, several network on chip architectures have offered mechanisms to perform the operation, while conforming to resource constraints of the network on chip paradigm. Multicast communication in majority of these networks on chip is implemented by establishing a connection between source and all multicast destinations before the message transmissioncommences. Establishing the connections incurs an overhead and, therefore, is not desirable; in particular in latency sensitive services such as cache coherence.To address high performance multicast communication, this research presents Quarc, a novel network on chip architecture. The Quarc architecture targets an area-efficient, low power, high performance implementation. The thesis covers a detailed representation ofthe building blocks of the architecture, including topology, router and network interface.The cost and performance comparison of the Quarc architecture against other network on chip architectures reveals that the Quarc architecture is a highly efficient architecture.Moreover, the thesis introduces novel performance models of complex traffic patterns, including multicast and quality of service-aware communication.