The main objective of this thesis is to perform a comprehensive simulation study of thestatistical variability in well scaled fully depleted ultra thin body silicon on insulator(FD-UTB SOI) at nanometer regime. It describes the design procedure for template FDUTBSOI transistor scaling and the impacts of statistical variability and reliability thescaled template transistor.The starting point of this study is a systematic simulation analysis based on a welldesigned32nm thin body SOI template transistor provided by the FP7 projectPULLNANO. The 32nm template transistor is consistent with the InternationalTechnology Roadmap for Semiconductor (ITRS) 2009 specifications. The wellestablished3D ‘atomistic’ simulator GARAND has been employed in the designing ofthe scaled transistors and to carry out the statistical variability simulations. Followingthe foundation work in characterizing and optimizing the template 32 nm gate lengthtransistor, the scaling proceeds down to 22 nm, 16 nm and 11 nm gate lengths usingtypically 0.7 scaling factor in respect of the horizontal and vertical transistordimensions. The device design process is targeted for low power applications with acareful consideration of the impacts of the design parameters choice including buriedoxide thickness (TBOX), source/drain doping abruptness (σ) and spacer length (Lspa). Inorder to determine the values of TBOX, σ, and Lspa, it is important to analyze simulationresults, carefully assessing the impact on manufacturability and to consider thecorresponding trade-off between short channel effects and on-current performance.Considering the above factors, TBOX = 10nm, σ = 2nm/dec and Lspa = 7nm have beenadopted as optimum values respectively.ivThe statistical variability of the transistor characteristics due to intrinsic parameterfluctuation (IPF) in well-scaled FD-UTB SOI devices is systematically studied for thefirst time. The impact of random dopant fluctuation (RDF), line edge roughness (LER)and metal gate granularity (MGG) on threshold voltage (Vth), on-current (Ion) and draininduced barrier lowering (DIBL) are analysed. Each principal sources of variability istreated individually and in combination with other variability sources in the simulationof large ensembles of microscopically different devices. The introduction of highk/metal gate stack has improved the electrostatic integrity and enhanced the overalldevice performance. However, in the case of fully depleted channel transistors, MGGhas become a dominant variability factor for all critical electrical parameters at gate firsttechnology. For instance, σVth due to MGG increased to 41.9 mV at 11nm gate lengthcompared to 26.0 mV at 22nm gate length. Similar trend has also been observed in σIon,increasing from 0.065 up to 0.174 mA/μm when the gate length is reduced from 22 nmdown to 11 nm. Both RDF and LER have significant role in the intrinsic parameterfluctuations and therefore, none of these sources should be overlooked in thesimulations.Finally, the impact of different variability sources in combination with positive biastemperature instability (PBTI) degradation on Vth, Ion and DIBL of the scalednMOSFETs is investigated. Our study indicates that BTI induced charge trapping is acrucial reliability problem for the FD-UTB SOI transistors operation. Its impact notonly introduces a significant degradation of transistor performance, but also acceleratesthe statistical variability. For example, the effect of a late degradation stage (at trapdensity of 1e12/cm2) in the presence of RDF, LER and MGG results in σVth increase to36.9 mV, 45.0 mV and 58.3 mV for 22 nm, 16 nm and 11 nm respectively from theoriginal 29.0 mV, 37.9 mV and 50.4 mV values in the fresh transistors.
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Scaling and variability in ultra thin body silicon on insulator (UTB SOI) MOSFETs
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