Parallelization has moved in recent years into the mainstream compilers, and the demandfor parallelizing tools that can do a better job of automatic parallelization is higher thanever. During the last decade considerable attention has been focused on developing programmingtools that support both explicit and implicit parallelism to keep up with thepower of the new multiple core technology. Yet the success to develop automatic parallelisingcompilers has been limited mainly due to the complexity of the analytic processrequired to exploit available parallelism and manage other parallelisation measures suchas data partitioning, alignment and synchronization.This dissertation investigates developing a programming tool that automatically paralleliseslarge data structures on a heterogeneous architecture and whether a high-level programminglanguage compiler can use this tool to exploit implicit parallelism and make useof the performance potential of the modern multicore technology. The work involved thedevelopment of a fully automatic parallelisation tool, called VSM, that completely hidesthe underlying details of general purpose heterogeneous architectures. The VSM implementationprovides direct and simple access for users to parallelise array operations on theCell’s accelerators without the need for any annotations or process directives. This workalso involved the extension of the Glasgow Vector Pascal compiler to work with the VSMimplementation as a one compiler system. The developed compiler system, which is calledVP-Cell, takes a single source code and parallelises array expressions automatically.Several experiments were conducted using Vector Pascal benchmarks to show the validityof the VSM approach. The VP-Cell system achieved significant runtime performanceon one accelerator as compared to the master processor’s performance and near-linearspeedups over code runs on the Cell’s accelerators. Though VSM was mainly designed fordeveloping parallelising compilers it also showed a considerable performance by runningC code over the Cell’s accelerators.
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A new parallelisation technique for heterogeneous CPUs