Towards Very Large Scale Analog (VLSA): Synthesizable Frequency Generation Circuits.

ADPLLs;PLLs;All-digital;Synthesizable Analog;Radios;Clock Generators;Oscillators;Electrical Engineering;Engineering;Electrical Engineering

Faisal, MuhammadFlynn, Michael ;

University of Michigan

关键词: ADPLLs;    PLLs;    All-digital;    Synthesizable Analog;    Radios;    Clock Generators;    Oscillators;    Electrical Engineering;    Engineering;    Electrical Engineering;   

Others  :  https://deepblue.lib.umich.edu/bitstream/handle/2027.42/109027/mufaisal_1.pdf?sequence=1&isAllowed=y

瑞士|英语

来源: The Illinois Digital Environment for Access to Learning and Scholarship

【 摘 要 】

Driven by advancement in integrated circuit design and fabrication technologies, electronic systems have become ubiquitous. This has been enabled powerful digital design tools that continue to shrink the design cost, time-to-market, and the size of digital circuits. Similarly, the manufacturing cost has been constantly declining for the last four decades due to CMOS scaling.However, analog systems have struggled to keep up with the unprecedented scaling of digital circuits. Even today, the majority of the analog circuit blocks are custom designed, do not scale well, and require long design cycles.This thesis analyzes the factors responsible for the slow scaling of analog blocks, and presents a new design methodology that bridges the gap between traditional custom analog design and the modern digital design. The proposed methodology is utilized in implementation of the frequency generation circuits – traditionally considered analog systems. Prototypes covering two different applications were implemented. The first synthesized all-digital phase-locked loop was designed for 400-460 MHz MedRadio applications and was fabricated in a 65 nm CMOS process. The second prototype is an ultra-low power, near-threshold 187-500 kHz clock generator for energy harvesting/autonomous applications. Finally, a digitally-controlled oscillator frequency resolution enhancement technique is presented which allows reduction of quantization noise in ADPLLs without introducing spurs.