Analog to Digital Conversion Techniques for nanometer CMOS.

ADC;Digital Calibration;Nanometer CMOS;Giga-samples Per Second;Analog-to-Digital Converter;GS/S;Electrical Engineering;Engineering;Electrical Engineering

Pernillo, Jorge A.Wentzloff, David D. ;

University of Michigan

关键词: ADC;    Digital Calibration;    Nanometer CMOS;    Giga-samples Per Second;    Analog-to-Digital Converter;    GS/S;    Electrical Engineering;    Engineering;    Electrical Engineering;   

Others  :  https://deepblue.lib.umich.edu/bitstream/handle/2027.42/97792/cjorge_1.pdf?sequence=1&isAllowed=y

瑞士|英语

来源: The Illinois Digital Environment for Access to Learning and Scholarship

【 摘 要 】

This work investigates new approaches to analog-to-digital conversion that are suited for end-of-the-roadmap CMOS, and which also deliver orders-of-magnitude improvements in speed and energy efficiency.We break analog-to-digital conversion down to its essence and simplify the process of analog-to-digital conversion to its most basic form. This allows us to take advantage of the tremendous digital capability of nanometer processes and then implement the analog circuitry in the simplest way. We propose three ADC structures that enable high performance with low transistor gain and, low-precision comparators aided by digital processingFirst, a 1.5GS/s 7b flash ADC is presented. We advance a comparator redundancy technique by employing random and deliberate mismatch to set the comparator thresholds and eliminate the need for a low-impedance high-precision resistor ladder. Unusually, the proposed technique exploits large random variation in comparator offset. This enables the use of low precision dynamic comparators that can be optimized for speed.Second, a 9b 1GS/s 2-stage pipeline ADC is presented. This architecture achieves high performance with a low-gain op-amp and low accuracy comparators. A reduced MDAC gain relaxes the op-amp gain and bandwidth requirements and trades MDAC output swing for reduced op-amp power. This technique is assisted by a comparator redundancy scheme that decouples the 2nd stage sub-ADC performance from comparator matching requirements. A simple code-search algorithm calibrates the sub-ADCs and at the same time corrects any ADC errors from finite op-amp gain, offset and non-linearity. Digital trimming of a delay chain eliminates mismatch in the 1st stage sampling paths to provide a simple, low power alternative to a dedicated front-end S/H. Third, a 9b 2GS/s two-times interleaved pipeline ADC is presented. This architecture leverages op-amp sharing and 2nd stage sub-ADC sharing between two time-interleaved MDACs to reduce power and area. Furthermore, this technique eliminates the need for correcting ADC errors due to gain and offset mismatch between channels.