Phase Shifter and LNA Design for Satellite Communication

LNA;Phase Shifter;Satellite Communication;Low Noise Amplifier;RFIC;Reflective Type Phase Shifter;RTPS

Jeevananthan, Luxsumiadvisor:Safavi-Naeini, Safieddin ; affiliation1:Faculty of Engineering ; Safavi-Naeini, Safieddin ;

University of Waterloo

关键词: Low Noise Amplifier;    RTPS;    Master Thesis;    Reflective Type Phase Shifter;    Phase Shifter;    RFIC;    LNA;    Satellite Communication;   

Others  :  https://uwspace.uwaterloo.ca/bitstream/10012/13430/1/Jeevananthan_Luxsumi.pdf

瑞士|英语

来源: UWSPACE Waterloo Institutional Repository

【 摘 要 】

Phased arrays are being used in satellite communication systems in order to provide wireless data to mobile vehicles, ships and even aircrafts. This thesis focuses on the design of phase shifter, which is designed for the transmitter chain and low noise amplifier, which will be used in the receiver chain. The phase shifter is controlled using a digital-to-analog controller. This gives rise to quantization lobes which can fail the spectrum efficiency test. Careful analysis indicates that a minimum phase resolution needed for this application is around 6-bit. This research reviews various integrated circuit phase shifter topologies to come up with one that will meet the specifications for this system. A combination of reflective-type phase shifter and switch-type phase shifter is designed using 65-nm CMOS technology to provide a full 360 degree phase shift range with no power consumption. The measured insertion loss is about 13.05 +/- 2.75 dB at 29.75 GHz with a return loss of about 10 dB or greater. The antenna gain-to-temperature ratio, which is a common figure of merit used in satellite communication, must be met on the receiver side of the phased array system. Through link budget analysis, it was decided that two low noise amplifiers are needed to satisfy the specified gain-to-noise ratio; one off-chip low noise amplifier that is closer to the antenna and another on-chip low noise amplifier. This alleviates the constraints on both low noise amplifiers and allows for a more simple and cost-efficient design. This research focuses on the design of the on-chip low noise amplifier using 130-nm CMOS technology. The receiver chain operates in k-band; thus, the low noise amplifier is designed at 20 GHz. A gain of about 21 dB is achieved, with an output return loss above 10 dB, a 1-dB compression point at -23 dBm and a nominal power consumption of about 6.84 mW. The simulated noise figure for this low noise amplifier design is about 3.7 dB.