学位论文详细信息
A Study on the Acceleration of Arrival Curve Construction and Regular Specification Mining using GPUs
GPU;Acceleration;Arrival Curves;Specification Mining;Nested Word;Timed Regular Expression;Data Analytics;Execution Traces
Benann Rajendra, Nirmal Joshiaffiliation1:Faculty of Engineering ; advisor:Fischmeister, Sebastian ; Fischmeister, Sebastian ;
University of Waterloo
关键词: Arrival Curves;    Timed Regular Expression;    Execution Traces;    Master Thesis;    Specification Mining;    Nested Word;    Acceleration;    Data Analytics;    GPU;   
Others  :  https://uwspace.uwaterloo.ca/bitstream/10012/14284/1/BenannRajendra_NirmalJoshi.pdf
瑞士|英语
来源: UWSPACE Waterloo Institutional Repository
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【 摘 要 】

Data analytics is a process of examining datasets using various analytical and statistical techniques. Several tools have been proposed in the literature to extract hidden patterns, gather insights and build mathematical models from large datasets.However, these tools have been known to be computationally demanding as the datasets become larger over time. Two such recently proposed tools are the construction of arrival curves from execution traces and mining specifications in the form of regular expressions from execution traces. Though the architectures in CPUs have extensively improved over the years to execute such computationally intensive tasks, further enhancements have been impeded due to increased heat dissipation. This has resulted in enabling parallel computing through GPUs as a vastly favorable alternative to overcome the computational challenges.In this thesis, we present an exploratory work on applying GPU computing to the construction of arrival curves and mining specifications in the form of regular expressions as case studies. The novel approaches taken for each of the case studies are first presented followed by the algorithmic breakdown to expose the parallelism involved. Lastly, experiments using commodity GPUs are presented to showcase the significant speedups obtained in comparison to the equivalent non-parallel implementations.

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