Cache Coherency for Symmetric Multiprocessor Systems on Programmable Chips

Electrical & Computer Engineering;FPGA;SOPC;SMP;cache coherency

Hung, Austin

University of Waterloo

关键词: Electrical & Computer Engineering;    FPGA;    SOPC;    SMP;    cache coherency;   

Others  :  https://uwspace.uwaterloo.ca/bitstream/10012/764/1/a2hung2004.pdf

瑞士|英语

来源: UWSPACE Waterloo Institutional Repository

【 摘 要 】

Rapid progress in the area of Field-Programmable Gate Arrays (FPGAs) has led to the availability of softcore processors that are simple to use, and can enable the development of a fully working system in minutes. This has lead to the enormous popularity of System-On-Programmable-Chip (SOPC) computing platforms.These softcore processors, while relatively simple compared to their leading-edge hardcore counterparts, are often designed with a number of advanced performance-enhancing features, such as instruction and data caches. Moreover, they are designed to be used in a uniprocessor or uncoupled multiprocessor architecture, and not in a tightly-coupled multiprocessing architecture.As a result, traditional cache-coherency protocols are not suitable for use with such systems.This thesis describes a system for enforcing cache coherency on symmetric multiprocessing (SMP) systems using softcore processors.A hybrid protocol that incorporates hardware and software to enforce cache coherency is presented.