Towards Efficient Hardware Implementation of Elliptic and Hyperelliptic Curve Cryptography

Elliptic Curve Cryptography;Hyperelliptic Curve Cryptography;Hardware Implementation;Electrical and Computer Engineering

Ismail, Marwa Nabil

University of Waterloo

关键词: Elliptic Curve Cryptography;    Hyperelliptic Curve Cryptography;    Hardware Implementation;    Electrical and Computer Engineering;   

Others  :  https://uwspace.uwaterloo.ca/bitstream/10012/6833/1/Ismail_Marwa_Nabil.pdf

瑞士|英语

来源: UWSPACE Waterloo Institutional Repository

【 摘 要 】

Implementation of elliptic and hyperelliptic curve cryptographic algorithms has been thefocusof a great deal of recent research directed at increasing efficiency. Elliptic curve cryptography (ECC) was introduced independently by Koblitz and Miller in the 1980s. Hyperelliptic curve cryptography (HECC), a generalization of the elliptic curve case, allows a decreasing field size as the genus increases.The work presented in this thesis examines the problems created by limited area, power, andcomputation time when elliptic and hyperelliptic curves are integrated into constrained devices such as wireless sensor network (WSN) andsmart cards. The lack of a battery in wireless sensor network limits the processing power of these devices, but they still require security. It was widely believed that devices with such constrained resources cannot incorporate a strong HECC processor for performing cryptographic operations such as elliptic curve scalar multiplication (ECSM) or hyperelliptic curve divisor multiplication (HCDM). However, the work presented in this thesis has demonstratedthe feasibility of integrating an HECC processor into such devicesthrough the use of the proposed architecture synthesis and optimization techniques for several inversion-free algorithms. The goal of this work is to develop a hardware implementation of binary elliptic and hyperelliptic curves. The focus is on the modeling of three factors: register allocation, operation scheduling, and storage binding. These factors were then integrated into architecture synthesis and optimizationtechniques in order to determinethe best overall implementation suitable for constrained devices. The main purpose of the optimization is to reduce the area and power. Through analysis of the architecture optimization techniques for both datapath and control unit synthesis, the number of registers was reduced by an average of 30%. The use of the proposed efficient explicit formula for the different algorithms also enabled a reduction in the number of read/write operations from/to the register file, which reduces the processing power consumption. As a result, an overall HECC processor requires from 1843 to 3595 slices for a Xilinix XC4VLX200 and the total computation time is limited to between 10.08 ms to 15.82 ms at a maximum frequency of 50 MHz for a varity ofinversion-free coordinate systems in hyperelliptic curves. The value of the new model has been demonstrated with respect to its implementation in elliptic and hyperelliptic curve crypogrpahic algorithms, through both synthesis and simulations.In summary, a framework has been provided for consideration ofinteractions with synthesis and optimization through architecture modeling for constrained enviroments. Insights have also been presented with respect to improvingthe design process for cryptogrpahic algorithms through datapath and control unit analysis.