Wafer-To-Wafer Alignment Method

Jung-Kubiak, Cecile [Inventor]Reck, Theodore [Inventor]Thomas, Bertrand [Inventor]Lin, Robert H [Inventor]Peralta, Alejandro [Inventor]Gill, John J [Inventor]Lee, Choonsup [Inventor]Siles, Jose V [Inventor]Toda, Risaku [Inventor]Chattopadhyay, Goutam [Inventor]

关键词: WAFERS;    ALIGNMENT;    PINS;    INTERFERENCE FIT;    PATENTS;   

RP-ID  :  US-Patent-10,100,858, US-Patent-Appl-SN-15/337,745

学科分类：机械工程学

美国|英语

来源: NASA Technical Reports Server

【 摘 要 】

A silicon alignment pin is used to align successive layer of component made in semiconductor chips and/or metallic components to make easier the assembly of devices having a layered structure. The pin is made as a compressible structure which can be squeezed to reduce its outer diameter, have one end fit into a corresponding alignment pocket or cavity defined in a layer of material to be assembled into a layered structure, and then allowed to expand to produce an interference fit with the cavity. The other end can then be inserted into a corresponding cavity defined in a surface of a second layer of material that mates with the first layer. The two layers are in registry when the pin is mated to both. Multiple layers can be assembled to create a multilayer structure. Examples of such devices are presented.