Yearlong 500 °C Operational Demonstration of Up-Scaled 4H-SiC JFET Integrated Circuits

Neudeck, Philip G ; Spry, David J ; Krasowski, Michael J ; Prokop, Norman F ; Beheim, Glenn M ; Chen, Liang-Yu ; Chang, Carl W

关键词: CHIPS (MEMORY DEVICES);    DESIGN ANALYSIS;    DIGITAL ELECTRONICS;    DURABILITY;    FIELD EFFECT TRANSISTORS;    INTEGRATED CIRCUITS;    JFET;    METAL OXIDE SEMICONDUCTORS;    RANDOM ACCESS MEMORY;    SEMICONDUCTORS (MATERIALS);    SILICON CARBIDES;    THRESHOLD VOLTAGE;    TRANSISTORS;    WAFERS;   

RP-ID  :  GRC-E-DAA-TN56142

学科分类：电子与电气工程

美国|英语

来源: NASA Technical Reports Server

【 摘 要 】

This work describes recent progress in the design, processing, upscaling, and testing of 500°C durable two-level interconnect 4H-SiC JFET IC technology undergoing development at NASA Glenn Research Center. For the first time, stable electrical operation of semiconductor ICs for 1 year (8760 hours) at 500°C in air atmosphere is reported. These groundbreaking durability results were attained on two-level interconnect JFET demonstration ICs with 175 or more transistors on each chip. This corresponds to a more than 7-fold increase in 500°C-durable circuit complexity from the 24 transistor ring oscillator ICs reported at HiTEC 2016.