Process for Fabrication of Superconducting Vias for Electrical Connection to Groundplane in Cryogenic Detectors

Denis, Kevin L [Inventor]

关键词: SOI (SEMICONDUCTORS);    ELECTRIC CONNECTORS;    CRYOGENICS;    FABRICATION;    WAFERS;    SILICON;    SINGLE CRYSTALS;    SUPERCONDUCTIVITY;    PATENTS;    INVENTIONS;   

RP-ID  :  US-Patent-9,865,795, US-Patent-Appl-SN-15/281,371

学科分类：电子与电气工程

美国|英语

来源: NASA Technical Reports Server

【 摘 要 】

Disclosed are systems, methods, and non-transitory computer-readable storage media for fabrication of silicon on insulator (SOI) wafers with a superconductive via for electrical connection to a groundplane. Fabrication of the SOI wafer with a superconductive via can involve depositing a superconducting groundplane onto a substrate with the superconducting groundplane having an oxidizing layer and a non-oxidizing layer. A layer of monocrystalline silicon can be bonded to the superconducting groundplane and a photoresist layer can be applied to the layer of monocrystalline silicon and the SOI wafer can be etched with the oxygen rich etching plasma, resulting in a monocrystalline silicon top layer with a via that exposes the superconducting groundplane. Then, the fabrication can involve depositing a superconducting surface layer to cover the via.