Understanding and Mitigating Multicore Performance Issues on theAMD Opteron Architecture

Levesque, John ; Larkin, Jeff ; Foster, Martyn ; Glenski, Joe ; Geissler, Garry ; Whalen, Stephen ; Waldecker, Brian ; Carter, Jonathan ; Skinner, David ; He, Helen ; Wasserman, Harvey ; Shalf, John ; Shan,Hongzhang ; Strohmaier, Erich

COLLABORATION - CrayInc.

关键词: Efficiency;    Multicore Supercomputer Processor Performance;    Manufacturers;    Computer Architecture;    Processing;   

DOI  :  10.2172/918496
RP-ID  :  LBNL--62500
RP-ID  :  DE-AC02-05CH11231
RP-ID  :  918496

美国|英语

来源: UNT Digital Library

【 摘 要 】

Over the past 15 years, microprocessor performance hasdoubled approximately every 18 months through increased clock rates andprocessing efficiency. In the past few years, clock frequency growth hasstalled, and microprocessor manufacturers such as AMD have moved towardsdoubling the number of cores every 18 months in order to maintainhistorical growth rates in chip performance. This document investigatesthe ramifications of multicore processor technology on the new Cray XT4?systems based on AMD processor technology. We begin by walking throughthe AMD single-core and dual-core and upcoming quad-core processorarchitectures. This is followed by a discussion of methods for collectingperformance counter data to understand code performance on the Cray XT3?and XT4? systems. We then use the performance counter data to analyze theimpact of multicore processors on the performance of microbenchmarks suchas STREAM, application kernels such as the NAS Parallel Benchmarks, andfull application codes that comprise the NERSC-5 SSP benchmark suite. Weexplore compiler options and software optimization techniques that canmitigate the memory bandwidth contention that can reduce computingefficiency on multicore processors. The last section provides a casestudy of applying the dual-core optimizations to the NAS ParallelBenchmarks to dramatically improve their performance.