FPIX core architecture and the preFPIX2 chip: Architecture and simulation

Hoff, Jim ; Mekkaoui, Abder ; /Fermilab

Fermi National Accelerator Laboratory

关键词: Modifications;    Testing;    99 General And Miscellaneous//Mathematics, Computing, And Information Science;    Transistors Computing;    Geometry;   

DOI  :  10.2172/15011747
RP-ID  :  FERMILAB-TM-2110
RP-ID  :  AC02-76CH03000
RP-ID  :  15011747

美国|英语

来源: UNT Digital Library

【 摘 要 】

preFPIX2 is a developmental step in the evolution of the final BTeV pixel architecture. It is a smaller version of a fully functional FPIX Core. It is a necessary step between FPIX1 and FPIX2 mostly for monetary reasons. Both FPIX1 and FPIX2 must be bump bonded to 18 x 160 arrays of ATLAS pixel detectors. Therefore, since each pixel is 50 {micro}m by 400 {micro}m, each FPIX chip cannot possibly be smaller than 7.2 mm by 8 mm. Since such a large chip is expensive, the collaborators are only being conservative by producing smaller versions of full FPIX chips when testing different ideas. Most importantly, preFPIX2 continues a progression towards smaller and smaller device geometries. FPIX0 was developed using Hewlett-Packard's 0.8 {micro}m CMOS process. FPIX1 was developed using Hewlett-Packard's 0.5 {micro}m CMOS process. FPIX2 will be developed in IBM's 0.25 {micro}m process or TSMC's 0.25 {micro}m process or in both processes. The major objectives of the development of preFPIX2 are to test the ability to successfully develop deep submicron IC chips and to test the capabilities of both the TSMC and IBM processes. The goal of reducing the process geometry is to take advantage of the higher and higher radiation tolerances they provide. To further the goal of high radiation tolerance, FPIX2 will be developed using radiation tolerant design techniques, in particular, enclosed transistors. preFPIX2 is the first functional chip developed at Fermilab to use such techniques. Finally, preFPIX2 has been developed to test a number of algorithmic modifications to the original read-out control developed in FPIX1. The FPIX1 readout architecture, also called the Command Driven Architecture, has been highly successful in all tests. However, it was decided that it could be improved substantially and simplified dramatically without changing it fundamentally. The purpose of this paper is to describe in detail this new version of the Command Driven Architecture and to describe a concept that is somewhat new to FPIX--the division of labor between the Core and the Periphery.