An Equal Area Comparison of Embedded DRAM and SRAM Memory

Keltcher, Paul ; Richardson, Stephen ; Siu, Stuart

HP Development Company

关键词: Embedded DRAM;    Chip Multiprocessor;    CMP;    Cache Hierarchy;    Pageable Memory;   

RP-ID  :  HPL-2000-53

学科分类：计算机科学（综合）

美国|英语

来源: HP Labs

【 摘 要 】

Recent architectures in academia and industry have explored placing multiple processors on a single chip, but a consensus has not emerged on the memory architecture. The recent availability of embedded DRAM (EDRAMS) has further complicated the formula. In this investigation, we present a new and comprehensive comparison of four very different memory technologies in the same framework: SRAM cache, SRAM configured as pageable memory, EDRAM configured as cache, and EDRAM configured as pageable memory. In addition, these experiments investigate tradeoffs between two levels of on-chip memory, given constant silicon area: as the level one capacity increases, the level two capacity decreases. Having four processors on a single die, each with its own set of level one caches, helps exaggerate the effective memory tradeoffs. 14 Pages