Progressive degradation in a-Si:H/SiN thin film transistors

THIN SOLID FILMS

卷:427

Article; Proceedings Paper

Merticaru, AR ; Mouthaan, AJ ; Kuper, FG

关键词: degradation;    charge trapping;    interface states;    modelling;   

DOI  :  10.1016/S0040-6090(02)01245-2

来源: Elsevier

【 摘 要 】

In this paper we present the study of gate-stress induced degradation in a-Si:H/SiN TFTs. The drain current transient during gate bias stress (forward or reverse bias) and subsequent relaxation cannot be fitted with the models existent in the literature but it shows to be described by a progressive degradation model (PDM). According to PDM the degradation of the electrical response is a combined effect of a fast interface traps generation and a slow charge trapping at the created defect sites and existing bulk defects in a-SiN:H transitional region. (C) 2002 Elsevier Science B.V. All rights reserved.

【 授权许可】

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