Hardware implementation of a fault-tolerant Hopfield Neural Network on FPGAs

NEUROCOMPUTING

卷:171

Article

Antonio Clemente, Juan¹  Mansour, Wassim²  Ayoubi, Rafic³  Serrano, Felipe¹  Mecha, Hortensia¹  Ziade, Haissam⁴  El Falou, Wassim⁵  Velazco, Raoul² 

[1] Univ Complutense Madrid, Comp Architecture Dept, E-28040 Madrid, Spain

[2] INPG, TIMA Lab, Grenoble, France

[3] Univ Balamand, Dept Comp Engn, Tripoli, Lebanon

[4] Lebanese Univ, Fac Engn 1, Elect & Elect Dept, Tripoli, Lebanon

[5] Lebanese Univ, Fac Engn 1, Tripoli, Lebanon

关键词: Artificial Neural Network (ANN);    Hopfield Neural Network (HNN);    Single Event Upset (SEU);    Single Event Transient (SET);    FPGA;    Fault tolerance;   

DOI  :  10.1016/j.neucom.2015.06.038

来源: Elsevier

【 摘 要 】

This letter presents an FPGA implementation of a fault-tolerant Hopfield Neural Network (HNN). The robustness of this circuit against Single Event Upsets (SEUs) and Single Event Transients (SETs) has been evaluated. Results show the fault tolerance of the proposed design, compared to a previous non-fault-tolerant implementation and a solution based on triple modular redundancy (TMR) of a standard HNN design. (C) 2015 Elsevier B.V. All rights reserved.

【 授权许可】

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